This invention relates to a semiconductor memory device, and more particularly to a delay locked loop circuit with wide operation range and improved locking time and performance.
In general, high speed semiconductor memory devices such as Rambus DRAM, synchronous DRAM, synchlink DRAM and double data rate (DDR) DRAM generate internal clock signals which are used in their internal circuits by using an external clock signal. However, the phase difference between the external clock signal and the internal clock signal is made due to physical delay. The prior semiconductor memory device uses the delay locked loop circuit which remove the phase difference between the internal clock signal and the external clock signal to solve the problem of set-up time and hold time.
FIG. 1A shows a block diagram of the delay locked loop circuit of a DDR DRAM. The delay locked loop circuit includes: a plurality of delay circuits 10 of delay chain which delay an input signal IN for a selected time and providing it to the next delay circuit; and a shift register 12 for generating select signals for respectively selecting any one of the delay circuits to the delay circuits.
FIG. 1B shows a circuit diagram of the delay circuit of FIG.1A. The delay circuit includes: a NAND gate NAND1 for receiving the input signal Input and the corresponding selection signal sel; a NAND gate NAND2 for receiving a power supply voltage Vcc and an output signal of the NAND gate NAND1; and an inverter IV1 for inverting an output signal of the NAND gate NAND2 to provide it to the next delay circuit.
In the delay locked loop circuit, the input signal Input is provided to one of delay circuits which is selected by the selection signal sel of the shift register 12 and delayed. The delayed input signal delayed through the selected delay circuit is passing through the next delay circuits and finally the internal clock signal is generated through the last delay circuit. Accordingly, when the last one of the delay circuits 10 is selected by the shift register 12, the delay time through the delay locked loop circuit becomes minimum value. On the other hand, when all the delay circuits 10 are selected by the shift resister 20, the delay time through the delay locked loop circuit becomes maximum value.
FIG. 1C is a graph showing the delay line characteristic of the prior delay locked loop circuit in FIG. 1A. The delay line characteristic is obtained in case where the delay locked loop circuit is constituted with the 128 delay circuits. As illustrated in the graph, the delay locked loop circuit having 128 delay chains has the superior linearity of the delay line.
However, so as to obtain the wider operation range than the prior delay locked loop circuit of FIG. 1A, the delay chains far more than 128 are necessary so that lay out is limited. Besides, although the minimum delay chains are used to increase accuracy of a synchronous signal, at least one delay circuit should be used in the delay locked loop circuit so that it is limited to embody the high performance delay locked loop circuit.
FIG. 2A shows a circuit diagram of a delay locked loop circuit in a synclink DRAM. The delay locked loop circuit includes a plurality of delay circuit 20 of delay chain; a multiplexer 22 for receiving output signals of the delay circuits 20 and selecting one of the output signals.
FIG. 2B shows a circuit diagram of the delay circuit in FIG. 2A. The delay circuit 20 is constituted with a differential amplifier. If a control signal Ctrlp is at logic low level and a control signal Ctrln is at logic high level, a power supply voltage Vcc is applied through transfer gates TM1 and TM2 and a current pass is formed to a ground terminal Vss through a NMOS transistor N3. Therefore, the delay circuit 20 operates.
At this time, if the input signals INp and INn are applied to gates of NMOS transistors N1 and N2, the delay circuit 20 outputs the differential amplified-signal through output terminals OUTn and OUTp by the voltage difference between the input signals INn and Inp.
FIG. 2C is a graph showing the delay line characteristic of the prior delay locked loop circuit in FIG. 2A. In the prior delay locked loop circuit, total delay time due to delay line is adjusted to one period(T cycles) of an input clock. If the delay circuit 20 is constituted with 32 delay chains, the multiplxer 22 selects any one of 32 reference clocks.
However, because the delay circuit 20 is designed under the consideration of minimum period and maximum period, the delay locked loop circuit having plural delay chains has a limit in design rule.
Besides, in case where the delay locked loop circuit uses 6-bit digital to analog converter (DAC), if the operation range (maximum delay time minus minimum delay time) is 10 ns, then the delay time per one step becomes 10 ns/64step=156.25 ps.
However, the delay time per one step of the 6-bit DAC in the area of inferior linearity, that is, in the minimum delay area has a difference ten times more than the delay time per one step in the maximum delay area. This phenomenon is understood from the tangent line of the characteristic graph of delay line in FIG. 2B.
Accordingly, if the operation range of the prior delay locked loop circuit of FIG. 2A becomes very narrower, it maintains very superior linearity. On the contrary, if the operation range of the prior delay locked loop circuit becomes wider, linearity becomes deteriorated so that the efficiency is degraded.
FIG. 3A shows a circuit diagram of a delayed locked loop circuit in a Rambus DRAM. The delay locked loop circuit includes four delay circuits 30 operating at 1/2 period of an input clock; a multiplexer 32 selecting two signals of the respective two output signals from the 4 delay circuits; and a phase mixer 34 for selecting one of two signals from the multiplexer 32 and providing the selected one as a final clock signal.
FIG. 3B shows a circuit diagram of the delay circuit in FIG. 3A. The delay circuit 30 includes a phase mixer 34 for receiving a clock input signal Input and a delayed clock input signal through two amplifiers 35 and for providing a mixed signal of the clock input signal Input and delayed input signal. The phase mixer 34 outputs the mixed signal of two input signals with a differential current control.
As shown in FIG. 3C, if the maximum current is Ifast and the minimum current is Islow, the delay circuit 30 outputs the input clock signal Input as an output clock signal which is directly provided to the phase mixer 34 without delay through the amplifiers 35. On the other hand, if the maximum current is Islow and the minimum current is Ifast, the delay circuit 30 outputs the input clock signal delayed through the amplifiers 35. If the currents Ifast and Islow have the same value, the delay circuit 30 outputs a clock signal which has the intermediate phase between the non-delayed input clock signal and the delayed input cock signal through the amplifiers 35.
Herein, the differential control current is adjusted by a 8-bit DAC. If the operation range is divided into 256 steps, an amount of delay per one step can be obtained. Accordingly, if the operation range becomes wider, the delay time per step becomes larger so that the performance in design can not obtained.
Besides, because the operation range of the delay circuit 30 in FIG. 3B is determined by the capacitors C1 and C2 and the amplifiers 35, there is a limit to design the delay circuit which operates at a slow rate.